| ASIC Design - From Concept to Product |
Date : 15-17th June 2011 ( 9am-5pm)
Course Fee :
S$1200.00
Discount : Sign up two persons and the third person enjoys 50%
discount.
Master Trainer :
Ms. Meenu Sarin
Synopsis
This course is aimed to provide an
opportunity for the participant to acquire comprehensive technical and business
insight into the ASIC world. As most of
these aspects also hold true for general IC design, this course will also
greatly benefit an IC Design Engineer. Application Specific Integrated Circuit
(ASIC) is a major topic of interest in the highly competitive field of VLSI
circuits where each industry player tries to outdo the other by introducing a
niche and differentiated product ahead of the competition. While products
assembled from off-the-shelf components are faster to reach the market, they
ride on an already existing product wave. With ASICs, however, one can be the
forerunner and tap into the initial and major chunk of the market window
grossing high revenues. The exclusive design rights also provide an added advantage.
This course will provide a basic
understanding & a holistic view of the complete ASIC design flow. It will
enable the participant to understand the basics involved in various phases of
ASIC design with an appreciation of the links and dependencies across them.
Industry insights shared in this training help the participant appreciate the
ASIC design flow in a real working world. The
course is structured into modules. Short
interactive workshops within the course facilitate in making this an interesting,
interactive learning experience. Participants will be exposed to issues cited
from real industry experience. This
course will be delivered by a senior VLSI consultant with extensive industry
experience in supporting & managing ASIC projects on a global scale. What You Will Learn
After
going through this training program, the participant would have learnt -
Different
aspects and phases of the complete ASIC design flow -
These
include ü Basics of an ASIC design library ü Logic simulation and synthesis ü Floor plan, Place & Route, Design for
Manufacturability ü Design Verification, Design for Testability ü Low power design methodologies ü Insight into ASIC technology and market
trends -
Dependencies
and links across various design phases – this, in turn, will facilitate him in
comprehending how decisions made in one phase affects the other -
Be
ready to handle details of each design phase Who Should Attend
-
EEE engineers who would like to start working
in ASIC design -
ASIC
Customer support engineers, Business Development engineers, Program Managers Prerequisite
Basic
engineering know how. 1-2 years experience in IC design/support is preferable. Course Methodology
This course is conducted in a seminar
room. The course will include brief interactive workshops like sessions
to encourage participation and facilitate learning. Each participant will
receive a set of course material. There are no lab sessions. Course Structure
The
course is organized into modules to facilitate participants to attend a
specific module(s) as per their interest/need. To extract maximum benefit from
the course however, participation in all modules is recommended.
-
Standard
cell based ASIC -
Semi-custom
ASIC and Full custom ASIC -
Basics
of IC Design Flow -
Some
definitions -
Generic
Technology Aspects & Trends
-
Definition,
Library Architecture (With basic introduction to SSIs, IOs,
Memories, IPs; general circuits used like Flip flops, latches, combinational circuits, RAMs,
ROMs etc. will be included) -
Library
Cell Representations -
Cell
views (logical description, timing information, derating data, capacitance
information, power and area information) -
Global
views (max capacitance, interconnect info, max power and derating information) -
Library
Characterization (Standard load, trip points, parasitic caps,
input slew rate, timing equation, delay calculation) -
Library
Validation -
Trends
in Library architecture (Power, speed optimization, drive, contents
changing with technology and trends)
1.
Logic Simulation -
Simulation
modes (behavioral, functional, static timing analysis, gate level simulation) -
Net
capacitance -
Cell
model (primitive, library, macro/IP) and test bench -
SDF
in simulation -
Limitations
of logic simulation -
STA
2.
Logic Synthesis -
Logic
synthesis in the design flow -
HDL and Synthesis – some HDL guidelines -
Constraints
and operating conditions -
Memory
Synthesis -
Timing
driven synthesis
1.
Floorplan, Placement
& Routing, Finishing Floorplan -
Goal,
objective -
Hierarchical
Design -
I/O
and Power planning -
Core
limited and pad limited design -
Clock
Planning -
Grouping
and Regioning Placement & Routing, Finishing -
Goals & Objectives -
Timing
driven placement/Physical Design flow -
Information
formats -
Routing
(Global & detailed routing, clock routing, power routing) -
Back
Annotation, Circuit extraction -
Design
checks, Mask preparation 2.
DFM -
Need
for DFM -
Yield
categories -
Yield
Optimization (Critical Area Analysis, Chemical Mechanical Polishing,
Lithography, Compliance Check)
-
Need
for Verification -
Functional
Verification (Simulation, Formal Verification, Coverage –
Code, Functional, Assertion) -
Timing
Verification – STA, SSTA -
Physical
Verification – DRC, LVS, Parasitic Extraction -
Design
For Test (DFT) Scan (Full scan, boundary scan) Faults – Fault models, Fault collapsing, IDDQ
test and Fault simulation ATPG, At speed test BIST (LFSR, Signature Analysis) Test logic insertion
-
Sources
of power dissipation (Static, Short circuit, dynamic) -
Power
distribution considerations (Temperature, package, Voltage drop,
Electromigration) -
Low
power design techniques and methodologies (levels of low power optimization,
includes, MSV, MTCMOS, VTCMOS, encoding, logic reduction, clock gating etc.) -
Guidelines
for low power design
-
Basic
economics involved in ASIC development -
ASIC
Program Flow -
Key
factors to be considered at ASIC start up -
Selecting
technology, library, IPs, package etc. -
Die
size estimation, power estimation -
Design
interfaces -
What
is an ASIC program -
Different
functions -
Documentation,
check lists, sign-offs -
Issues
seen during ASIC implementation -
Guidelines
for effective ASIC program management
-
Some
definitions -
Shift
in ASIC technology & the underlying reasons -
Insight
into Structured ASICs/Platform ASICs -
IPs
used in Platform ASIC -
Cell
based ASIC vs. Platform ASIC -
Some
Industry examples illustrating the trend Course Instructor
Ms. Meenu Sarin is a microelectronics professional with over 21 years’ experience in
the microelectronics industry across various facets of operations &
across geographies like Europe, India, Singapore, Greater China and Australia and with special focus in the semi-custom ASIC environment. She has registered
her company, VLSI Consultancy, in Singapore from where she consults offering
techno-commercial services to the semiconductor industry. She has conducted
in-house training courses and public workshops in various countries including
Singapore, Malaysia, Hong Kong and India besides delivering talks in
universities. She is also a founding member and an Executive
Board Member of the Singapore Semiconductor Industry Association (www.ssia.org.sg) From 1997-2002, Meenu
was a Technical Marketing Manager in STMicroelectronics (STM)/Singapore with
focus on Telecom segment. In this role, she was responsible for Business
Development and Program Management for STM’s semicustom ASIC projects in Asia
Pacific. Meenu also worked as a Program Manager in charge of
managing various semi-custom projects with customers in the Asia-Pacific
Region. Before her move to STM
Singapore, Meenu worked at STM India from 1991 to 1997. As a Design Manager for Library Design Group,
she was responsible for growing and managing a 30 member strong team involved
in design and development of semi-custom digital libraries in various
technologies across different platforms as per the market requirements and to
support designers in STM’s worldwide locations.
Prior to this, Meenu had been a Design Engineer for digital library
design and development at STM Italy for several years after she received her
engineering degree (Computer Engineering) from Delhi Institute of Technology,
India in 1988. |