| Reliability Of Integrated Circuit |
|
Reliability of Integrated Circuit Master Trainer : Dr
Jose Maiz Date : 20-22nd
May 2013 Location :
Singapore Target Audience
: Reliability Engineer, Quality Engineer, Design Engineer, Process
Engineer Reliability Fundamentals and scaling
principles •
Reliability life curve: defects vs intrinsic mechanisms •
Functional Yield to Reliability correlation •
Reliability Functions and indicators •
Reliability characterization methods and
strategies: Electrical, thermo-mechanical and moisture •
Acceleration, characterization and
classification of reliability failures •
The
use of test vehicles •
Scaling Principles and Reliability
implications •
Scaling trends •
Some
reliability strategies for Fabless companies Reliability of transistors •
CMOS
Transistor structure, operation and trends •
Polysilicon/SiO2 system vs HK+
MG. Comparisons and Reliability issues •
Integrity on gate dielectrics: Degradation
mechanisms, characterization and dependencies •
Hot
Carriers •
Transistor (in)stability.
NMOS/PMOS, SiO2 vs HK+MG. Circuit implications •
Plasma process induced damage •
HBTs:
Degradation mechanisms and characterization methods Reliability of the interconnect system •
Trends on Interconnect •
Al vs Cu and SiO2 vs low K ILDs.
Advantages and issues •
Electromigration in Al & Cu based interconnects:
Fundamentals, characterization and
dependencies •
Electromigration under Non DC and short line conditions •
ILD
integrity: Cu migration in the ILD, & dielectric integrity •
Metal
cracking and voiding •
Other
thermomechanical issues: ILD Cracking and delamination Interactions between Product Design, Design
Rules and the manufacturing process •
CMOS
Latch-up •
Description, origin and manifestation in CMOS
integrated circuits •
Electrical signatures and trigger mechanisms •
Interactions with layout design rules and
process •
Product requirements and characterization
methods •
Elimination, improvement and mitigation
strategies •
Electrostatic
Damage •
Origin, description and definitions •
Requirements and characterization methods •
Models and devices behavior under high
current pulses •
Failure modes & mechanisms •
Commonly used devices and methods for ESD
protection •
Single event Upsets and Soft Error •
Description, origin and history •
How
circuits get affected and errors result •
Requirements and characterization methods •
Mitigation options and strategies •
Impact of technology scaling About
Dr Jose Maiz Dr
Jose Maiz is an Intel Fellow and director of Logic Technology
Quality and Reliability. He joined Intel in 1983 and has contributed to the
development and reliability of 10 semiconductor technology generations.
Presently, he is responsible for identification of silicon reliability limiters
to scaling, and their resolution for Intel's next generation silicon logic
products. Dr.
Maiz graduated with a degree in physics from the University of Navarra in Spain
and received MSc. and PhD. degrees in Electrical
Engineering from the Ohio State University. He holds 10 patents and has 12 more
pending. He has authored or co-authored over 35 publications and conference
presentations, many of them invited and including two keynote addresses. He is
a senior member of the IEEE, recipient of multiple Intel awards, is a Fulbright
Scholar, has teaching appointments at CEI Europe and
serves in the Advisory boards of the CEIT research Institute and CIC Nanogune. Registration
Details Course Fee : S$1950.00 per pax Early bird discount of S$100.00 for
registration before 20th April 2013. Group discount of S$50.00 for group of 3
or more. Please email to
This e-mail address is being protected from spam bots, you need JavaScript enabled to view it
to book your
seat. |