COURSE OUTLINE

 

This course is designed for analog design engineers who are working with ADC/DAC

design.  Principles of high speed and nano-meter sigma delta design will be discussed. 

As power consumption is crucial in today’s design, several examples of sigma-delta

converters that are optimized for low-power will be presented. There are also analysis

and discussion on the architecture of high speed CMOS AD and DA converter. Last

but not least, various interference effects affecting the performance of ADC/DAC will

be covered in detail.

 

Day 1 - Principles

1.1 Deep Submicron IC Design

An overview of the trends and the problems for deep submicron and nano-meter

CMOS design are discussed. Several issues such as mismatch, importance of drain

area's etc are introduced. The different issues are discussed in later lectures in detail

 

1.2 Sigma Delta Principles

Introduction in sigma-delta techniques. The different topologies and effects are

discussed. Problems related to first order and higher order topologies are analysed.

Effects off finite gain, switch resistance and settling time are discussed.

 

1.3 High Speed Sigma Delta

The development of high data-rate modems such as aDSL systems, and the resulting

requirement for A/D converters with high bit accuracies (>15 bit) in combination with

a 1.1MHz signal bandwidth. The different design trade-offs and problems in the

design of high-speed D-S converters. The problems of the architecture selection, the

3V power supply requirement, and the resulting high switch on-resistance. Design

examples of high speed, high performance CMOS D-S data converters.

 

1.4 Nano-meter Sigma Delta Design

The design of Delta-Sigma converters in nano-meter CMOS result in different

topology selections and design requirements. In this lecture both the architecture and

circuit implementation structures such as amplifiers, switches and biasing circuit s are

explored for nano-meter technologies. Several design examples and performances are

analyzed and discussed.

 

Day 2 – High Speed ADC/DAC Design

2.1 Continuous Time Sigma Delta

Continuous time Delta-Sigma Converters For high accuracy Sigma-Delta (SD) ADC's

are very popular due to their robustness towards implementation in CMOS

technologies. However due to the typically switched capacitor (SC) implementation,

speed limitations and aliasing in telecom architectures limit their use. For that

continuous time (CT) implementations are investigated for telecom applications. In

this presentation an overview of the differences, advantages and disadvantages of CT

and SC SD are 
discussed. Due to the CT nature, jitter issues are becoming important.

For that low sensitive feed back (Vref) techniques are described. Some design cases

towards low voltage nano-meter technologies are studied.

 

2.2 Low voltage SD: Switched-Op Amp

The design of low-power Delta-Sigma converters involves the choice of the

oversampling ratio and the filter order. The resultant dynamic range also depends on

implementation aspects such as the amplifier schemes, the switches, etc. Several

examples are discussed of delta-sigma AD converters which have been optimized for

low power consumption and which run at supply voltages below 1 V.

 

2.3 High Speed AD

Analysis of CMOS AD architectures. Discussion of different topologies such as

folding, interpolating and averaging techniques.  Design cases of high performances

CMOS AD's are analysed. Different averaging techniques and the boundary problem

are studied.

 

2.4 High Speed DA

Analysis of CMOS DA architectures and the mismatch behaviour. Discussion of static

errors and lay-out issues. Discussion of the dynamic errors and circuit techniques to

improve it. Case study of a high speed CMOS DAC structure.

 

Day 3 – Interference Effects

3.1 Interference Effects: Coupling / Pinning Strategy

Different sources and their impact on coupling effects are analyzed. Both examples of

digital and analog circuit noise generating structures are presented. A brief discussion

of pinning strategy and substrate effects are discussed. Design rules and bondwire

effects are investigated.

 

3.2 Interference Effects: Mismatch

To reduce to effect, differential structures and circuits towards high PSRR are

commonly used. This however requires circuits with high CMRR, PSRR and

symmetrical topologies. Those are strongly related to the matching properties of the

schematic and lay-out. for that matching performances are analyzed followed by

CMRR relationships. Finally some lay-out considerations are presented.

 

3.3 Interference Effects: Differential and CMRR

Differential architectures require common mode feed backs. Different topologies are

discussed. Secondly CMRR is studied. Basic relationships and techniques to improve

the CMRR in circuit design are analysed.

 

3.4 Interference Effects: PSRR

Some EMC interference effects in integrating RF circuits are addressed and discussed.

The coupling mechanism of different building blocks to the sensitive RF circuits are

addressed. Design techniques for high power supply rejection ratio in basic analog

building blocks are studied.